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FEATURES Monolithic 10-Bit, 20 MSPS A/D Converter Low Power Dissipation: 1.0 W Signal-to-Noise Plus Distortion Ratio fIN = 1 MHz: 56 dB f IN = 10 MHz: 54 dB Guaranteed No Missing Codes On-Chip Track-and-Hold Amplifier 100 MHz Full Power Bandwidth High Impedance Reference Input Out of Range Output Twos Complement and Binary Output Data Available in Commercial and Military Temperature Ranges (See Military/Aerospace Reference Manual for Specifications)
2 VINA 26 VINB 27 THA
10-Bit, 20 MSPS Monolithic A/D Converter AD773A
FUNCTIONAL BLOCK DIAGRAM
REFIN REFGND 1 AVDD 4 AGND 5, 28 AVSS DV DD DGND DRV DD 6 24 3, 25 7, 22 DRGND 8, 21
THA
THA
A/D
A/D
DAC
A/D
DAC
CLOCK 23
TIMING CONTROL
CORRECTION LOGIC OUTPUT BUFFERS
AD773A
20 19 18 9 OTR MSB BIT 1 BIT 10 (MSB) (LSB)
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD773A is a monolithic 10-bit, 20 Msps analog-to-digital converter incorporating an on-board, high performance trackand-hold amplifier (THA). The AD773A converts video bandwidth signals without the use of an external THA. The AD773A implements a multistage differential pipelined architecture with output error correction logic. The AD773A offers accurate performance and guarantees no missing codes over the full operating temperature range. Output data is presented in binary and twos complement format. An out of range (OTR) signal indicates the analog input voltage is beyond the specified input range. OTR can be decoded with the MSB/MSB pins to signal an underflow or overflow condition. The high impedance reference input allows multiple AD773As to be driven in parallel from a single reference. The combined dc precision and dynamic performance of the AD773A is useful in a variety of applications. Typical applications include: video enhancement, HDTV, ghost cancellation, ultrasound imaging, radar and high speed data acquisition. The AD773A was designed using Analog Devices' ABCMOS-1 process which utilizes high speed bipolar and 2-micron CMOS transistors on a single chip. High speed, precision analog circuits are now combined with high density logic circuits. Laser trimmed thin film resistors are used to optimize accuracy and temperature stability. The AD773A is packaged in a 28-pin ceramic DIP and is available in commercial (0C to +70C) and military (-55C to +125C) grades.
1. On-board THA The high impedance differential input THA eliminates the need for external buffering or sample and hold amplifiers. The THA offers the choice of differential or single-ended inputs. Input current is typically 5 A. 2. High Impedance Reference Input The high impedance reference input (200 k) allows direct connection with standard +2.5 V references, such as the AD680, AD580 and REF43. 3. Output Data Flexibility Output data is available in bipolar offset and bipolar twos complement binary format. 4. Out of Range (OTR) The OTR output bit indicates when the input signal is beyond the AD773A's input range. 5. Military Temperature Range
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AD773A-SPECIFICATIONS
DC SPECIFICATIONS
Parameter RESOLUTION DC ACCURACY Integral Nonlinearity TMIN to TMAX Differential Linearity Error TMIN to TMAX Zero Error Gain Error No Missing Codes ANALOG INPUT Input Range Input Current Input Capacitance REFERENCE INPUT Reference Input Resistance Reference Input LOGIC INPUT High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = DVDD) Low Level Input Current (VlN = 0 V) Input Capacitance LOGIC OUTPUTS High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) POWER SUPPLIES Operating Voltages AVDD AVSS DVDD, DRVDD Operating Current IAVDD IAVSS IDVDD IDRVDD1 POWER CONSUMPTION2 POWER SUPPLY REJECTION TEMPERATURE RANGE Specified (J/K)
NOTES 1 CL = 15 pF. 2 100% production tested. Specifications subject to change without notice. See Definition of Specifications for additional information.
(TMIN to TMAX with AVDD = +5 V 5%, AVSS = -5 V 5%, DVDD = +5 V DRVDD = +5 V 5%, VREF = +2.500 V unless otherwise noted)
Min 10 AD773AJ Typ Max Min 10
5%,
AD773AK Typ
Max
Units Bits LSB LSB LSB LSB % FSR % FSR
0.75 0.75 0.5 0.5
0.75
2
0.75 1 0.5 3.5 0.5 3.0 GUARANTEED 1 5
1 5
20 10 50
20 10
V p-p A pF k Volts V V A A pF V V
50
200 2.5
200 2.5
+3.5 -10 -10 10 +2.4 +0.4 +0.5 +10 +10
+3.5 -10 -10 10 +2.4 +0.4 +0.5 +10 +10
+4.75 -5.25 +4.75 65 -115 10 10 1.0 10 0
+5.25 -4.75 +5.25 80 -140 20 15 1.2 18 +70
+4.75 -5.25 +4.75 65 -115 10 10 1.0 10 0
+5.25 -4.75 +5.25 80 -140 20 15 1.2 18 +70
Volts Volts Volts mA mA mA mA W mV/V C
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AD773A AC SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE1 Signal-to-Noise plus Distortion (S/N+D) Ratio fIN = 1 MHz fIN = 10 MHz Effective Number of Bits (ENOB) fIN = 1 MHz fIN = 10 MHz Total Harmonic Distortion (THD) fIN = 1 MHz fIN = 10 MHz Spurious Free Dynamic Range2 Full Power Bandwidth Intermodulation Distortion (IMD)3 Second Order Products Third Order Products Differential Phase Differential Gain Transient Response Overvoltage Recovery Time
(TMIN to TMAX with AVDD = +5 V 5%, AVSS = -5 V 5%, DVDD, = +5 V 5%, DRVDD = +5 V VREF = +2.500 V unless otherwise noted, fSAMPLE = 20 MSPS, flN amplitude = -0.5 dB)
Min AD773AJ Typ Max Min AD773AK Typ Max
5%,
Units
52 50
56 54 9.0 8.7 -67 -65 70 100 -69 -64 0.2 0.5 25 25 -57 -54
54 51
56 54 9.0 8.7 -67 -65 70 100 -69 -64 0.2 0.5 25 25 -59 -55
dB dB Bits Bits dB dB dB MHz dB dB Degree % ns ns
NOTES 1 For typical dynamic performance curves at f SAMPLE = 20 Msps see Figures 2 through 7. 2 fIN = 1 MHz. 3 fa = 1.0 MHz, fb = 1.05 MHz. Specifications subject to change without notice.
TIMING SPECIFICATIONS DRV
Conversion Rate Clock Period Clock High Clock Low Output Delay Aperture Delay Aperture Jitter Pipeline Delay (Latency) tCLK tCH tCL tOD
(for all grades TMIN to TMAX with AVDD = +5 V 5%, AVSS = -5 V 5%, DVDD = +5 V 5%, VREF = +2.500 V unless otherwise noted, fSAMPLE = 20 MSPS) DD = +5 V
Min 50 24.5 24.5 20 7 9 4 Typ Max 20
5%,
Units Msps ns ns ns ns ns ps Clock Cycles
Symbol
N VIN N+1
tC
N N+1
CLOCK
t CH
BIT 1-10 MSB, OTR
t CL
t OD
DATA N DATA N+1
Figure 1. AD773A Timing Diagram
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AD773A
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE1
Parameter AVDD AVSS VINA, VINB DVDD, DRVDD AGND AVDD CLK REFIN Junction Temperature Storage Temperature Lead Temperature (10 sec)
With Respect to AGND AGND AGND DGND, DRGND DGND, DRGND DVDD, DRVDD DVDD, DRVDD REFGND, AGND
Min -0.5 -6.5 -6.5 -0.5 -1.0 -6.5 -6.5 -0.5 -65
Max Units +6.5 +0.5 +6.5 +6.5 +1.0 +0.5 +0.5 +6.5 +150 +150 V V V V V V V V C C Model
Temperature Range
Description
Package Option2
AD773AJD 0C to +70C AD773AKD 0C to +70C
28-Pin Ceramic DIP D-28 28-Pin Ceramic DIP D-28
NOTES 1 See Military/Aerospace Reference Manual for AD773ASD/883B specifications. 2 D = Ceramic DIP.
PIN DESCRIPTION Symbol AGND AVDD AVSS MSB Pin No. Type Name and Function 5, 28 4 3, 25 19 P P P DO Analog Ground. +5 V Analog Supply. -5 V Analog Supply. Inverted Most Significant Bit. Provides twos complement output data format. Out of Range is Active HIGH on the leading edge of Code 0 or the trailing edge of Code 1023. See Output Data Format Table II. Most Significant Bit. Data Bit 2 through Data Bit 9. Least Significant Bit. Clock Input. The AD773A will initiate a conversion on the falling edge of the clock input. See the Timing Diagram for details. +5 V Digital Supply. +5 V Digital Supply for the output drivers. Digital Ground. Digital Ground for the output drivers. REFGND is connected to the ground of the external reference. REFIN is the external 2.5 V reference input, taken with respect to REFGND. (+) Analog input signal to the differential input THA. (-) Analog input signal to the differential input THA.
+300 C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
PIN CONFIGURATION
OTR
20
DO
REFGND REFIN AVSS AV DD AGND DGND DRV DD DRGND BIT 10 (LSB) BIT 9 BIT 8
1 2 3 4 5 6 7 8 9 10 11
28 27 26 25
AGND V INB V INA AVSS DV DD CLK DRV DD DRGND OTR MSB BIT 1 (MSB) BIT 2 BIT 3 BIT 4
BIT 1 (MSB) BIT 2-BIT 9 BIT 10 (LSB) CLK
18 17-10 9 23
DO DO DO DI
AD773A
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17 16 15
DVDD DRVDD DGND DRGND REFGND REFIN
24 7, 22 6 8, 21 1 2
P P P P AI AI
BIT 7 12 BIT 6 BIT 5 13 14
VINA VINB
26 27
AI AI
Type: AI = Analog Input; DI = Digital Input; DO = Digital Output; P = Power.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD773A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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Definitions of Specifications- AD773A
INTEGRAL NONLINEARITY (INL) INTERMODULATION DISTORTION (IMD)
Linearity error refers to the deviation of each individual code from a line drawn from "zero" through "full scale." The point used as "zero" occurs 1/2 LSB before the first code transition. "Full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line.
DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
ZERO ERROR
With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa+fb) and (fa-fb) and the third order terms are (2fa+fb), (2fa-fb), (fa+2fb) and (fa-2fb). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. The two signals are of equal amplitude and the peak value of their sums is -0.5 dB from full scale. The IMD products are normalized to a 0 dB input signal.
DIFFERENTIAL GAIN
The major carry transition should occur for an analog value 1/2 LSB below analog common. Zero error is defined as the deviation of the actual transition from that point.
GAIN ERROR
The percentage difference between the output amplitudes of a small high frequency sine wave at two stated levels of a low frequency signal on which it is superimposed.
DIFFERENTIAL PHASE
The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale. The last transition should occur 1 1/2 LSB below the nominal positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
POWER SUPPLY REJECTION
The difference in the output phase of a small high frequency sine wave at two stated levels of a low frequency signal on which it is superimposed.
TRANSIENT RESPONSE
The time required for the AD773A to achieve its rated accuracy after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY TIME
One of the effects of power supply variation on the performance of the device will be a change in gain error. The specification shows the maximum gain error deviation as the supplies are varied from their nominal values to their specified limits.
SIGNAL-TO-NOISE PLUS DISTORTION (S/N+D) RATIO
The time required for the ADC to recover to full accuracy after an analog input signal 150% of full scale is reduced to 50% of the full-scale value.
APERTURE DELAY
S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
The difference between the switch delay and the analog delay of the THA. This effective delay represents the point in time, relative to the falling edge of the CLOCK input, that the analog input is sampled.
APERTURE JITTER
ENOB is calculated from the following expression: S/N+D = 6.02N + 1.76, where N is equal to the effective number of bits.
TOTAL HARMONIC DISTORTION (THD)
The variations in aperture delay for successive samples.
PIPELINE DELAY (LATENCY)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.
SPURIOUS FREE DYNAMIC RANGE
The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every clock cycle.
FULL POWER BANDWIDTH
The peak spurious or peak harmonic component is the largest spectral component excluding the input signal and dc. This value is expressed in decibels relative to the rms value of a fullscale input signal.
The input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input.
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AD773A-Dynamic Characteristics
60
0
50 AIN= -6dB 40
S/N+D - dB
-20 FO
AIN= -0.3dB
AMPLITUDE - dB
-40
30
THD -60
20
-80
10
2ND HARMONIC 3RD HARMONIC 1E+08 1E+09
0 1E+05
1E+06
1E+07
1E+08
-100 1E+05
1E+06
FREQUENCY - Hz
1E+07 FREQUENCY - Hz
Figure 2. S/N+D vs. Input Frequency, fCLK = 20 MSPS
Figure 5. Harmonic Distortion vs. Input Frequency, fCLK = 20 MSPS: Small Signal
0 -10
0
-20
AMPLITUDE - dB
-20 -30 -40 -50 -60 -70
fIN = 1MHz fIN AMPLITUDE = -0.5 THD = -67dB S/(N+D) = 56dB 2ND HARMONIC = -78dB 3RD HARMONIC = -73dB
CMR - dB
-40
-60
-80
-80 -90
-100 1E+05
1E+06
1E+07
1E+08
-100 0 1.3 2.6 3.8 5.1 6.4 7.7 9 10 FREQUENCY - MHz
FREQUENCY - Hz
Figure 3. CMR vs. Input Frequency, fCLK = 20 MSPS
Figure 6. Typical FFT Plot of AD773A, fCLK = 20 MSPS, fIN = 1 MHz at 1 V p-p
0
20
0 FO
-10 -20 -30 fIN = 9.9MHz fIN AMPLITUDE = -0.5 THD = -63dB S/(N+D) = 54dB 2ND HARMONIC = -70dB 3RD HARMONIC = -66dB
AMPLITUDE - dB
-20
AMPLITUDE - dB
-40 -50 -60 -70 -80
-40
-60
THD
-80 2ND HARMONIC -100 1E+05 1E+06 3RD HARMONIC
-90
1E+07 FREQUENCY - Hz
1E+08
1E+09
-100 0 1.3 2.5 3.8 5.1 6.4 7.6 8.9 10 FREQUENCY - MHz
Figure 4. Harmonic Distortion vs. Input Frequency, fCLK = 20 MSPS: Full Power
Figure 7. Typical FFT Plot of AD773A, fCLK = 20 MSPS, fIN = 9.9 MHz at 1 V p-p
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AD773A Theory of Operation
The AD773A uses a pipelined multistage architecture with a differential input, fast settling track-and-hold amplifier (THA). Traditionally, high speed ADCs have used parallel, or flash architectures. When compared to flash converters, multistage architectures reduce the power dissipation and die size by reducing the number of comparators. For example, the AD773A uses 48 comparators compared to 1023 comparators for a 10-bit flash architecture. The AD773A's main signal path transmits differential current mode signals. Low impedance current summing techniques are employed, increasing speed by reducing sensitivity to parasitic capacitances. Pipelining allows the stages to operate concurrently and maximizes system throughput. The input THA is followed by three 4-bit conversion stages. At any given time, the first stage operates on the most recent sample, while the second stage operates on a signal dependent on the previous sample. This process continues throughout all three stages. The twelve digital bits provided by the three 4-bit stages are combined in the correction logic to produce a 10-bit representation of the sampled analog input. Pipeline delay, or latency, is four clock cycles. New output data is provided every clock cycle and is provided in both binary and twos complement format. The AD773A will flag an out-ofrange condition when the analog input exceeds the specified analog input range.
INPUT CONDITIONING
In some cases, it may be appropriate to buffer the input source, add dc offset, or otherwise condition the input signal of the AD773A. Choosing an appropriate op amp will vary with system requirements and the desired level of performance. Some suggested op amps are the AD9617, AD842, and AD827. Figure 9 shows a typical application where a unipolar signal is level shifted to the bipolar input range of the AD773A. Note that the reference used with the AD773A can also provide a noise-free voltage source to generate the dc offset.
2.49k +2.5V 499
ANALOG INPUT (0 TO +1V)
499
VINA
2.49k
Figure 9. Unipolar to Bipolar Input Connection
DIFFERENTIAL INPUT CONNECTIONS
Operating the AD773A with fully differential inputs offers the advantage of rejecting common-mode signals present on both VINA and VINB. The full-scale input range of VINA and VINB when driven differentially is 250 mV p-p as shown in Table I.
Table I. AD773A's Maximum Differential Input Voltage
Applying the AD773A
DRIVING THE AD773A INPUT
The AD773A may be driven in a single-ended or differential fashion. VINA is the positive input, and VINB is the negative input. In the single-ended configuration either VINA or VINB is connected to Analog Ground (AGND) while the other input is driven with a full-scale input of 500 mV p-p. An inverted mode of operation can he achieved by simply interchanging the input connections. Both inputs of the AD773A, VINA and VINB, are high impedance and do not need to be driven by a low impedance source. Note, however, that as the source impedance increases, the input node becomes more susceptible to noise. The increased noise at the input will degrade performance. A 10 pF capacitor across VINA and VINB as shown in Figure 8 is recommended to bypass high frequency noise.
VINA +250 mV -250 mV
VINB -250 mV +250 mV
VINA-VINB +500 mV -500 mV
In some applications it may be desirable to convert a singleended signal to a differential signal before being applied to the AD773A. Figure 10 shows a single-ended to differential video line driver capable of driving doubly terminated cables.
510 510 75 ANALOG INPUT (500mV) VINB 75
510 510 75 VINA 75
500mV 26 10pF VINA
AD773A
Figure 10. Single-Ended to Differential Connection
27 VINB
Figure 8. AD773A Single-Ended Input Connection
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AD773A
REFERENCE INPUT
1.08
POWER - W
The AD773A's high impedance reference input allows direct connection with standard voltage references. Unlike the resistor ladder requirements of a flash converter the AD773A's single pin, high impedance input can be driven from one low cost, low power reference. The high impedance input allows multiple AD773A's to be driven from one reference thus minimizing drift errors. Figure 11 shows the AD773A connected to the AD680. The AD680 is a single supply, low power, low cost 2.5 V reference with performance specifications ideally suited for the AD773A. The low pass filter minimizes the AD680's wideband noise. Other recommended 2.5 V references are the AD580 and REF43.
2 V IN
1.07
1.06
1.05
1.04
1.03
1.02 1.0E+07
1.5E+07 SAMPLE FREQUENCY - Hz
2.0E+07
Figure 13. Power Dissipation vs. Sample Frequency
22 2 REF IN 10F 0.1F
AD680
V OUT 6 GND 4
EQUIVALENT ANALOG INPUT CIRCUIT
AD773A
1 REF GND
Figure 11. Recommended AD773A to AD680 Connection
CLOCK INPUT
The AD773A's pipelined architecture operates on both the rising and falling edges of the clock input. A low jitter, symmetrical clock will provide the highest level of performance. The recommended logic family to drive the clock input is HC. The AD773A's minimum clock half cycle may necessitate the use of an external divide-by-two circuit as shown in Figure 12. Power dissipation will vary with input clock frequency as shown in Figure 13.
+5V
The AD773A equivalent analog input circuit is shown in Figure 14. The typical input bias current is 5 A, while input capacitance is typically 5 pF. In the single-ended input configuration one input is connected to AGND while the second input is driven to full scale ( 500 mV). Under nominal conditions the collector of the input transistor is at +1.15 V. This allows signals to be offset by up to +0.65 V without significantly degrading performance. In the negative direction, the emitter of the input transistor should not drop below -1.25 V. Therefore, signals can be offset by -0.65 V without significant performance degradation. Figure 15 shows signal-to-noise ratio vs. common-mode input voltage.
+5V 1.0mA +1.15V 5pF
AIN 1Vp-p
AD773A
R D Q
-1.25V 1.0mA
74XX74
40MHz Q S CLK
-5V
Figure 14. Equivalent Analog Input Circuit
60 AIN = -0.3dB
+5V
Figure 12. Divide-by-Two Clock Circuit
50
AIN = - 6dB
40
S/N+D - dB
30
20
10
0 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2
0.0
0.2
0.4
0.6
0.8
1.0
COMMON MODE INPUT VOLTAGE - V
Figure 15. S/N+D vs. Common-Mode Input Voltage, fCLK = 20 MSPS
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AD773A
EQUIVALENT REFERENCE INPUT CIRCUIT
The AD773A is designed to have a reference to analog input voltage ratio of 2.5:1. When the AD773A is configured for single-ended operation a 2.5 volt reference input establishes a full-scale analog input voltage of 1 V p-p ( 500 mV with respect to VINB). Although the AD773A is specified and tested with VREF equal to 2.5 V and VIN equal to 500 mV the reference input voltage and analog input voltages can be changed. To optimize the AD773A's performance the 2.5:1 ratio should be maintained. The simplified model of the AD773A's reference input circuit is shown in Figure 16.
1.2
1.1 POWER - W 1 0.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 REFIN - V
AD773A
REFIN
R1
Figure 18. Power Dissipation vs. Reference Input Voltage, fCLOCK = 20 MSPS
TRANSIENT RESPONSE
VBIAS REFGND R3 R2 -5V A
Figure 16. Typical Reference Input Circuit
The 2.5 V external reference is applied across resistor R1 producing a current which in turn generates a voltage VBIAS. Multiple reference currents are generated from VBIAS and are used throughout the converter. R3 is used to cancel errors induced by the input bias current of the REFGND buffer. Figure 17 shows the SNR performance as the reference voltage is varied from its nominal value of 2.5 V. The input full-scale voltage is defined by the following equation,
Input Full-Scale Voltage =
The fast settling input THA accurately converts full-scale input voltage swings in under one clock cycle. The THA's high impedance, fast slewing performance is critical in multiplexed or dc stepped (charge coupled devices, infrared detectors) systems. Figure 19 show the AD773A's settling performance with an input signal stepped from -500 mV to 0 V. As can be seen, the output code settles to its final value in under one clock cycle.
1000
800
The power dissipation is modulated by variations in the reference voltage. Figure 18 shows the variation in power dissipation versus reference voltage.
60 AIN = -0.3dB 55
CODE
400
200
0 0 10 20 TIME - ns 30 40
50
S/N+D - dB
AIN = -6dB
Figure 19. Typical AD773A Settling Time
45
40
35
30 1.0
1.4
1.8
2.2
2.6
3.0
3.4
3.8
REFERENCE INPUT VOLTAGE - V
Figure 17. S/N+D vs. Reference Input Voltage, fCLK = 20 MSPS, fIN = 1 MHz
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EDOC
Reference Voltage 2 .5
600
AD773A
OUTPUT DATA FORMAT GROUNDING AND LAYOUT RULES
The AD773A provides both MSB and MSB outputs, delivering positive true offset binary and twos complement output data. Table II shows the AD773A's output data format.
Table II. Output Data Format
Analog Input VINA-VINB 499.5 mV 499 mV 0 mV -500 mV -500.5 mV Offset Binary 11 1111 1111 11 1111 1111 10 0000 0000 00 0000 0000 00 0000 0000
Digital Output Twos Complement 01 1111 1111 01 1111 1111 00 0000 0000 10 0000 0000 10 0000 0000
OTR 1 0 0 0 1
As is the case for any high performance device, proper grounding and layout techniques are essential in achieving optimal performance. (Note--Figures 22-26 are not to scale.) The analog and digital grounds on the AD773A have been separated to optimize the management of return currents in a system. It is recommended that a 4-layer printed circuit board (PCB) which employs ground planes and power planes be used with the AD773A. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout which prevents noise from coupling onto the input signal. The wide input bandwidth of the AD773A permits noise outside the desired Nyquist bandwidth to be sampled along with the desired signal. This can result in a higher overall level of spurious noise in the digitized output. Digital signals should not be run in parallel with the circuitry. It is also suggested that the traces associated with VINA and VINB be the same length. Separate analog and digital grounds should be joined together directly under the AD773A (see Figure 24). A solid ground plane under the AD773A is also acceptable if care is taken in the management of the power and ground return currents. A general "rule-of-thumb" for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry.
POWER SUPPLY DECOUPLING
OUT OF RANGE
An out-of-range condition exists when the analog input voltage is beyond the input range ( 500 mV) of the converter. [Note the AD773A has a 4 clock cycle latency.] OTR (Pin 20) is set low when the analog input voltage is within the analog input range. OTR is set HIGH and will remain HIGH when the analog input voltage exceeds the input range by 1/2 LSB from the center of the full-scale output codes. OTR will remain HIGH until the analog input is within the input range. Note that if the input is driven beyond +1.5 V, the digital outputs may not stay at +FS, but may actually fold back to midscale. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table III is a truth table for the over/under range circuit in Figure 20. Systems requiring programmable gain conditioning prior to the AD773A can immediately detect an out of range condition, thus eliminating gain selection iterations.
MSB OVER = "1" OTR
UNDER = "1" MSB
Figure 20. Overrange or Underrange Logic
Table III. Out-of-Range Truth Table
OTR 0 0 1 1
MSB 0 1 0 1
ANALOG INPUT IS In Range In Range Underrange Overrange
The analog and digital supplies of the AD773A have been separated to prevent the typically large transients associated with digital circuitry from coupling into the analog supplies (AVDD, AVSS). Each analog power supply pin should be decoupled with a 0.1 F capacitor located as close to the pin as possible. Additionally, 0.22 F capacitors for the DRVDD and DVDD supplies are required to adequately suppress high frequency noise. For optimal performance, surface-mount capacitors are recommended. The inductance associated with the leads of through-hole ceramic capacitors typically render them ineffective at higher frequencies. A complete system will also incorporate tantalum capacitors in the 10-100 F range to decouple low frequency noise and ferrite beads to limit high frequency noise. The digital supplies have also been separated into DRVDD and DVDD. The DRVDD pins provide power for the digital output drivers of the AD773A and are likely to contain high energy transients. Pin 22 should be decoupled directly to Pin 21 (DRGND) and Pin 7 should be decoupled directly to Pin 8 (DRGND) to minimize the length of the return path for these transients. A single +5 V supply is all that is required for DRVDD and DVDD, but decoupling DVDD with an RC filter network is suggested (see Figure 21). -10- REV. 0
AD773A
+5D CLOCK INPUT J2 TP10 C5 0.22 R4 49.9 TP9 R5 10 +5A C1 .1 4 ANALOG IN J1 TP11 R2 49.9 10pF 27 1 2 C3 .1 V INB MSB BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 BIT10 AV SS AV SS 26 10 24 22 21 23 20 19 18 17 16 15 14 13 12 11 10 9 3 25 C8 .1 6 7 8 9 10 11 12 13 14 15 29 C7 .1 2 4 C4 0.22 5 1 3 JP3 6 JP6 P1 40 PIN IDC CONN. R11 JP4 JP5 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 1 22 22 22 22 22 22 22 22 22 22 22 22
AV DD
U1 AD773A
DV DD DRV DD
V INA
DRGND CLK OUTRANGE
U5 74HC04
C2 10
REFGND REF IN
+5A
1 2 3 4
U3 AD680
V IN V OUT GND
R6 22 8 7 6 5
5 AGND 28 AGND 7 8 6
+5D C6 0.22 DRV DD DRGND DGND
-5A
FB1 +5VA AGND -5VA C12 FB2 FB3 +5VD .01 DGND C15 C9 .01 .01
C10 22
TP1 C11 +5A .1 TP2 .1 -5A
+5D C18 .1 TP4 +5D
BK SY
TP12 .1 C17 22 C16
30 31 32 33 34 35 36 37 38
16 17
39
+5D
FS
TP3
GND GND IOB VAA V AA
IOG IOR CMP REF
22 C13
28 27 26 25 24 23 22 21 20 19 18
CK G0 G1 G2 G3
G4 G5 G6 G7 G8 G9
C14
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 V AA
U2 ADV7122
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
5 4 3 2 1 44 43 42 41 40
R23 22
40
560 R10
J1 J2 R7 39
R8 39 C20 .1
C21 .1
+5D
U4 AD589
TP6 +5D TB5 C19 .1
TP7
R9 75
J3 TP8 ANALOG OUTPUT
Figure 21. AD773A Evaluation Board Schematic
Table IV. Components List
Reference Designator R2, R4 R5, R6, R11-R22 R7, R8 R9 R10 C1, C3-C8, C11, C14, C17-C21 C2 C9, C12, C15 C10, C13, C16 U1 U2 U3 U4 U5 FB1-FB3 REV. 0
Description Resistor, 1%, 49.9 Resistor, 5%, 22 Resistor, 5%, 39 Resistor, 5%, 75 Resistor, 5%, 560 Chip Cap, 0.1 F Capacitor, Tantalum, 10 F Chip Cap, 0.01 F Capacitor, Tantalum, 22 F AD773A ADV7122 AD680 AD589 74AS04 Ferrite Bead -11-
Quantity 2 14 2 1 1 14 1 3 3 1 1 1 1 1 3
AD773A
Figure 22. Component Side PCB Layout
Figure 23. Solder Side PCB Layout
-12-
REV. 0
AD773A
Figure 24. Ground Layer PCB Layout
Figure 25. Power Layer PCB Layout
REV. 0
-13-
AD773A
Figure 26. Silkscreen Layer PCB Layout
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Ceramic DIP Package (D-28)
0.005 (0.13) MIN 0.100 (2.54) MAX
28
15
0.610 (15.49) 0.500 (12.70) PIN 1 1 14 0.060 (1.52) 0.015 (0.38) 0.620 (15.75) 0.590 (14.99)
1.490 (37.85) MAX 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18)
0.150 (3.81) MIN
0.018 (0.46) 0.008 (0.20)
0.026 (0.66) 0.014 (0.36)
0.110 (2.79) 0.090 (2.29)
0.070 (1.78) 0.030 (0.76)
SEATING PLANE
-14-
REV. 0
AD773A
REV. 0
-15-
AD773A
-16-
C1865-7.5-12/93
REV. 0
PRINTED IN U.S.A.

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